The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having nonvolatile memory cells such as flash memory cells or mask ROM (read only memory) cells.
In recent years, as semiconductor memories for data storage or code storage of mobile telephones, digital cameras, etc., nonvolatile memories such as flash memories in which data is not lost even if the power supply is off or the battery goes dead are frequently used.
In some of such semiconductor memories, bit lines are connected with memory cells by a virtual grounding scheme in order to reduce the chip size without reducing the storage capacity. However, when the memory cells are connected with bit lines by a virtual ground system, adjacent memory cells connected with the same word line share a bit line. Because of this, there is a problem that for example at writing to one of adjacent memory cells, drain disturbance occurs in the other memory cell.
In order to solve such a problem, there is known a semiconductor memory device in which the memory cell array is divided into some areas, the number of memory cells existing in the row direction in one area is limited to 8, 16, or the like, and write operations are carried out for the memory cells in the area on a one-by-one basis. In such a semiconductor memory device, the number of bit lines in the case that the memory cell array is divided, for example, into areas each having n (n>2) memory cells is 2(n+1)/3n (0.75 when n=8) of that in a fixed bit line system in which each two memory cells share a fixed ground wire. Thus, reduction in the chip size resulting from reduction in the number of the bit lines can be expected.
As such a semiconductor memory device, there is a previously proposed one in which the memory cell array is electrically divided into a plurality of areas using transistors, and writing to memory cells is carried out for each of the areas (see JP 2002-279789 A for example).
However, the above conventional semiconductor memory device in which the memory cell array is divided into areas each including n memory cells in the row direction needs n write operations (8 when n=8), for all of the memory cells in the memory cell array. Because of this, there is a problem that the write time becomes extremely long. In addition, the above semiconductor memory device in which the memory cell array is divided using transistors has a problem that it needs an area to form the transistors, thereby increasing the chip area on the contrary.
By the way, the information stored in a nonvolatile memory cell is determined with the help of variation in the cell currents responsive to the storage condition, it is difficult from a structure viewpoint to get perfect agreement of cell current between a plurality of memory cells in which the same information is stored. Thus, it is a common occurrence that cell current values distribute in some degree of width even if the same information is stored in a plurality of memory cells. However, if the distribution of cell current values of memory cells in which certain information is stored overlaps with the distribution of cell current values of memory cells in which other information is stored, it is difficult to correctly determine information. For this reason, programmed verify operations are carried out so that the distribution of cell currents of memory cells in which certain information is stored does not overlap with the distribution of cell currents of memory cells in which other information is stored, in other words, there is a gap between the two distributions. However, there is a problem that a gap between the distributions of cell currents goes narrower as memories become smaller, operate at lower voltage, and store more-valued data. Furthermore, disturbance (disturbance by access to other memory cells), endurance (deterioration of the rewrite characteristic of memory cells resulting from increase of the number of rewrite operations), retention (deterioration of the property of retaining stored information resulting from variation with temperature, variation with time, etc.), etc. have different degrees of influence on a plurality of memory cells. Because of this, there is a problem that the distribution conditions of cell current values are different between, for example, word lines, and thereby gaps between the distributions deviate in position.
In order to solve such a problem, conventionally, there is a semiconductor memory device in which a reference cell or reference cells are provided every word line, and the current value of the reference cell or the average current value of the reference cells is set to a reference current value, and the cell current values of memory cells from which information is to be read are compared with the reference current values to determine the information (see JP 2004-273093 A). Specifically, two kinds of reference cells are connected to word lines, and are brought into correspondence with data 0 and data 1, the average current value of the reference cells being used as a reference current value. In addition, in consideration of cell current values varying due to disturbance, program verify operations are carried out to obtain the distribution of cell current values of memory cells, and the reference current value is reset, or changed based on the obtained distribution of cell current values of memory cells.
However, the conventional semiconductor memory device has a problem that reference cells are provided every word line, so that many reference cells are required, thereby increasing the chip area. Furthermore, there is a problem that since the memory cells are affected by disturbance until the program verify operations are carried out, information may be incorrectly determined.